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HDMI Switch ICs
BU16006KV, BU16018KV, BU16024KV, BU16027KV
No.10063EET01
Description These devices control are simple. It requires only 3.3V source and a few GPIO controls. Termination resistors (50) are integrated at all TMDS input port. When channel is not selected, TMDS input termination resistors are turned off and TMDS inputs are high impedance. These devices are also integrated equalizer circuit to adapt long cable and DDC active buffer function to isolate capacitance. Features 1) Supports 2.25 Gbps signaling rate for 480i/p, 720p, and 1080i/p resolution to 12-bit color depth 2) Compatible with HDMI 1.3a 3) 5V tolerance to all DDC and HPD_SINK inputs 4) Integrated active DDC buffer 5) Integrated switchable 50 termination resistors 6) Integrated equalizer circuit to adapt long cable 7) HBM ESD protection exceeds 10kV 8) 3.3V fixed supply 9) RoHS compatible
Applications Digital TV, Audio Video Receiver, Digital Projector, DVI or HDMI Switch Box
Line up matrix
Part No. BU16018KV BU16027KV BU16006KV BU16024KV Power Supply (V) 3 to 3.6 3 to 3.6 3 to 3.6 3 to 3.6 ESD (KV) 10 10 10 10 Input and Output 3 input 1 output 3 input 1 output 2 input 1 output 1 input 1 output Data rate (Gbps) 2.25 2.25 2.25 2.25 Hot Plug Control Yes Yes Yes Yes Termination Resistor switch Control Sync HPD Sync S1/S2 Sync HPD Sync HPD Switching Method GPIO GPIO GPIO DDC Buffer type Active Active Active Active Equalizer Fixed Fixed Fixed Fixed High speed mode Yes Yes (Always ON) Yes (Always ON) Yes Package VQFP80 VQFP64 VQFP64 VQFP48C RoHS Yes Yes Yes Yes
Other Line up
HDMI Switch adapted "Repeater" and "Source" Equipment
Part No. BU16025MUV Power Supply (V) 3 to 3.6 ESD (KV) 10 Input and Output 1 input 1 output Data rate (Gbps) 2.70 Hot Plug Control Yes Termination Resistor switch Control Sync OE Switching Method DDC Buffer type Active Equalizer Selectable High speed mode Yes Package VQFN48AV7070 RoHS Yes
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1/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Absolute Maximum Rating Over operating free-air temperature range (unless otherwise noted) Item Limits BU16006KV BU16018KV BU16024KV Power supply voltage(Vcc) -0.3+4.5 -0.3+4.5 -0.3+4.5 DDC, HPD_SINK input voltage -0.3+5.6 -0.3+5.6 -0.3+5.6 Differential input voltage +2.5+4.0 +2.5+4.0 +2.5+4.0 Control pin input voltage -0.3+4.0 -0.3+4.0 -0.3+4.0 Power dissipation 1000(*1) 1200(*2) 950(*3) Strage temperture range -55+125 -55+125 -55+125
(*1) When it's used by than Ta=25, it's reduced by 10.0mW/. (*2) When it's used by than Ta=25, it's reduced by 12.5mW/. (*3) When it's used by than Ta=25, it's reduced by 9.5mW/.
Technical Note
BU16027KV -0.3+4.5 -0.3+5.6 +2.5+4.0 -0.3+4.0 1000(*1) -55+125
Unit V V V V mW
(*1-3) 70mmx70mmx1.6mm glass epoxy board mount.Reverse Cu occupation rate15mmx15mm
Recommended Operating Conditions Symbol Parameter VCC Supply voltage TA Free-air temperature TMDS Differential Pins VIC Input common mode voltage, see Figure 2. VID(pp) Receiver peak-to-peak differential input voltage, see Figure 2. RVSADJ Resistor for TMDS compliant voltage swing range AVCC TMDS Output termination voltage, see Figure 1. RT Termination resistance, see Figure 1. Signaling rate Control Pins VIH LVTTL High-level input voltage VIL LVTTL Low-level input voltage HPD_SINK VIH High-level input voltage VIL Low-level input voltage RX (SDA[n],SCL[n]) VIH High-level input voltage VIL Low-level input voltage TX (SCL_SINK, SDA_SINK) VIH High-level input voltage VIL Low-level input voltage
Min. 3 0 VCC-0.6 150 4.60 3 45 2 GND 2.4 GND 2.4 GND 1.5 GND
Typ. 3.3 4.64 3.3 50 -
Max. 3.6 70 VCC+0.01 1560 4.68 3.6 55 2.25 VCC 0.8 5.5 0.8 5.5 0.8 5.5 0.35
Unit V V mVp-p k V Gbps V V V V V V V V
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2/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Electrical Specifications Over recommended operating conditions (unless otherwise noted) Symbol Parameter BU16006KV, BU16018KV BU16027KV BU16024KV BU16006KV, BU16018KV BU16027KV BU16024KV TMDS Differential Pins (A/B;Y/Z) BU16006KV, BU16027KV VOH Single-ended high-level output voltage BU16018KV, BU16024KV BU16018KV, BU16024KV Single-ended low-level output voltage BU16006KV, BU16027KV Single-ended BU16018KV, low-level BU16024KV swing voltage BU16018KV, BU16024KV Overshoot of output differential voltage Undershoot of output differential voltage Input termination resistance AVcc = Vcc, RT = 50 AVcc = Vcc, PRE = Vcc, RT = 50 AVcc = Vcc, PRE = 0.0V, RT = 50 AVcc = Vcc, RT = 50 AVcc = Vcc, RT = 50, Figure 2, AVcc = Vcc, PRE = Vcc, 50, See Figure 2, AVcc = Vcc, PRE = 0.0V, 50, See Figure 2, See Figure 2 See Figure 2 AVcc = Vcc = 3.3V, VA = Vcc-400mV, See Figure 2 See RT = RT = AVcc200 AVcc200 AVcc10 AVcc600 300 300 400 VB = 45 6% 12% 50 Test Condition VID = 400mV, RVSADJ = 4.64k RT = 50, AVcc = Vcc, Am/Bm = 2.25 Gbps HDMI data pattern, A1,/B1 = 225 MHz clock See Figure 2 VID = 400mV, RVSADJ = 4.64k RT = 50, AVcc = Vcc, Am/Bm = 2.25 Gbps HDMI data pattern, A1,/B1 = 225 MHz clock See Figure 2 Min. Limit Typ.(1) 120
Technical Note
Max. 150
Unit
mA
Icc
Supply current
-
140
170
mA
PD
Power Consumption
-
450
600
mW
-
480
700
mW
VOL
Avcc50 AVcc - 50 AVcc +10 Avcc400 460 460 600 15% 25% 55
mV mV mV mV mV mV mV 2xVswing 2xVswing
VSWING
Vod(O) Vod(U) RINT
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3/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Technical Note
Symbol DDC Input and output Tx IlKT1 IlKT2 IOHT IILT
Parameter
Test Conditions
Min.
Limits Typ.(1)
Max.
Unit
Input leak current Input leak current High-level output current Low-level input current BU16006KV BU16018KV BU16027KV
VI=5.5V VI=Vcc VO=3.6V VI=GND RL=4.7k
SELREF = NC
-10 -10 -10 -10 0.43 0.43 0.58 0.73 20
SELREF = NC
0.5 100 100 250 400 50 30 -
10 10 10 10 0.57 0.57 0.72 0.87 190 10 10 10 10 0.2 Vcc 0.4 10 10 45 45 100 80 10
A A A A V
VOLT
Low-level output voltage BU16024KV BU16006KV BU16018KV BU16027KV BU16024KV RL=4.7k
SELREF = GND SELREF =Vcc
V
RL=4.7k
mV
VOLT-VIL
Low-level input voltage below output low-level voltage
RL=4.7k
SELREF= GND SELREF = Vcc
-10 -10 -10 -10 2.4 0 -10 -10 -45 -45 10 5 -10
mV
Rx IlKR1 IlKR2 IOHR IILR Input leak current Input leak current High-level output current Low-level input current VI=5.5V VI=Vcc VO=3.6V VIL=GND Iout = 4mA IOH = -8mA IOL = 8mA VIH = Vcc VIL = GND VIH = Vcc VIL = GND VIH = 5.5V VIH = Vcc VIL = GND A A A A V V V A A A A A A A
VOLR Low-level output voltage HPD 1, HPD 2, HPD 3 VOH(TTL) High level output voltage VOL(TTL) Low level output voltage CONTROL PINS IIH High level input current IIL Low level input current CONTROL PINS (I2CEN, SELREF,) IIH IIL HPD_SINK IIH IIL High level input current Low -level input current High level input current Low level input current
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4/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Technical Note
Symbol TMDS Differential Pins (Y/Z) tPLH
Parameter BU16006KV, BU16018KV, BU16027KV BU16024KV BU16006KV, BU16018KV, BU16027KV BU16024KV BU16006KV, BU16027KV, BU16018KV BU16024KV BU16006KV, BU16018KV, BU16027KV BU16024KV BU16006KV, BU16018KV, BU16027KV BU16024KV BU16006KV, BU16018KV, BU16027KV
Test Condition
Min.
Limits Typ.(1)
Unit Max.
Propagation delay time low to high level output
AVCC = 3.3V, RT = 50 -
480 320 500 335 160 120 160 120 20 15 35 25
-
ps
tPHL
Propagation delay time low to high level output
ps
tr
Differential output signal rise time (20%-80%)
ps
tf
Differential output signal fall time (20%-80%)
ps
tsk(p)
Pulse skew (|tPHL - tPLH |)
ps
tsk(D)
Intra-pair differential skew, see Figure 3.
ps
BU16024KV DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) See Figure 4 Propagation delay time, low to high level output Tx to Rx
tpdLHTR(DDC)
RL = 4.7k, CL = 100pF, see Figure 5
-
650
-
ns
Propagation delay time, high to low level output Tx to Rx Propagation delay time, low to high level tpdLHRT(DDC) output Rx to Tx RL = 1.67k, CL = 400pF, Propagation delay time, high to low level see Figure 5 tpdHLRT(DDC) output Rx to Tx tr Tx(DDC) Tx output Rise time RL = 4.7k, CL = 100pF, see Figure 5 tf Tx(DDC) Tx output Fall time tr Rx(DDC) Rx output Rise time RL = 1.67k CL = 400pF tf Rx(DDC) Rx output Fall time tsx Select to switch output see Figure 4 tdis Disable time see Figure 4 ten Enable time see Figure 4 tsx(DDC) Switch time from SCLn to SCL_SINK CL=10pF CIO Input/output capacitance VI=0V Hot Plug Detect Pins Propagation delay time, low to high level tpdLH(HPD) CL=10pF output from HPD_SINK to HPDn(n=1,2,3) Propagation delay time, high to low level tpdHL(HPD) CL=10pF output from HPD_SINK to HPDn(n=1,2,3) Switch time from port select to the latest tsx(HPD) CL=10pF valid status of HPD Note: (1). All typical values are at 25 and with a 3.3V supply. tpdHLTR(DDC)
-
200 500 350 800 150 950 50 8 5 7 800 15 5 5 8
-
ns ns ns ns ns ns ns ns ns ns ns pF ns ns ns
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5/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Measurement Symbol And Circuit
Technical Note
AVcc RT
Zo = R T
TMDS Driver
RT
TMDS Receiver
Zo = R T
Figure 1 TMDS Output Driver
Vcc RINT RINT
RT Y VA A VID B VB VID = VA - VB Vswing = VY - VZ TMDS Driver TMDS Receiver CL 0.5pF Z VZ VY RT AVCC
VA
Vcc V
VB
Vcc-0.4 V 0.4 V VIC VID(pp) 0V -0.4 V tPLH 80% Vswing VOD(O) 0V Differential 20% tf tr VOD(U) 0% tPLH 100%
Figure 2 Test Circuit and Definitions
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6/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Technical Note
VY
VOH 50%
VZ
tsk(D)
VOL
Figure 3 Definition of Intra-Pair Differential Skew
A B A Port 2 B Port 3 A B Port 1 S1 Clocking S2
Vcc V Vcc-0.4 V Vcc-0.4 V Vcc V Vcc-0.4 V Vcc V VDD 2 VDD 0V
tsx
Y Output Z
tsx
75mV -75mV HI-Z 75mV -75mV
tdis
ten
Figure 4 TMDS Outputs Control Timing Definitions
VDD 2
HPD_SINK
VDD 2
HPD1 tpdHL(HPD) HPD2 HPD3 S1 S2 SDA_SINK SDA1
1.5V
tpdLH(HPD)
tsx(HPD)
2.4V
0V Vcc 2
tpdHLRT(DDC) tpdLHRT(DDC)
80% 20% 1.5V
tpdHLTR(DDC)
tpdLHTR(DDC)
tSX(DDC)
VDD
V IL 80% 20% 0V
SDA2 SDA3 tfTX(DDC) trTX(DDC) tfRX(DDC) TX to RX trRX(DDC) RX to TX
VDD
Figure 5 DDC and HPD Timing Definitions
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7/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Reference Data of BU16027KV/BU16006KV
Technical Note
Figure 6 Supply voltage(Vcc) vs. Supply current(Icc) of BU16006KV/BU16027KV [S1=H,S2=L]
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
8/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Pin Assignment and Block Diagram of BU16006KV
A11 B11
RINT
Technical Note
A12 B12
RINT
A13 B13
RINT
A14 B14
RINT
A14 B14 Vcc A13 B13 GND A12 B12 Vcc A11 B11 SCL1 SDA1 HPD1 Reserve1 S2
VCC TMD S RX
VCC
VCC
VCC
RINT TMD S RX
RINT TMD S RX
RINT TMD S RX
RINT
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A24 B24
32 31 30 29 28 27
RINT
RINT TMD S RX RINT TMD S RX RINT TMD S RX TMDS Drive TMDS Drive TMDS Drive
Y4 Z4 Y3 Z3 Y2 Z2 Y1
TMDS Drive
VCC RINT
Reserve2 HPD2 SDA2 SCL2 B21 A21 Vcc B22 A22 GND B23 A23 Vcc B24 A24 NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
S1 HPD_SINK SDA_SINK SCL_SINK GND Z1 Y1 Vcc Z2 Y2 GND Z3 Y3 Vcc Z4 Y4
A23 B23 A22 B22 A21 B21
VCC RINT
VCC RINT RINT TMD S RX
BU16006KV
(64-pin VQFP)
26 25 24 23 22 21 20 19 18 17
Z1 VSADJ
HPD1 HPD2
NC NC GND NC NC Vcc NC NC GND NC NC Vcc NC NC GND VSADJ
S1 S2 HPD_SINK
SCL1 SDA1 SCL2 SDA2
Control Logic
SCL_SINK SDA_SINK
Pin Explanation List Terminal Name No. A11, A12, A13, A14 39, 42, 45, 48 A21, A22, A23, A24 54, 57, 60, 63 B11, B12, B13, B14 38, 41, 44, 47 B21, B22, B23, B24 53, 56, 59, 62 3, 9, 15, 22, GND 28, 43, 58 HPD1 35 HPD2 50 HPD_SINK 31 Reserve1 34 Reserve2 49 SCL1 37 SCL2 52 SCL_SINK 29 SDA1 36 SDA2 51 SDA_SINK 30 S1, S2 32, 33 6, 12, 19, 25, Vcc 40, 46, 55, 61 VSADJ 16 Y1, Y2, Y3, Y4 26, 23, 20, 17 Z1, Z2, Z3, Z4 27, 24, 21, 18 I/O I I I I O O I I/O I/O I/O I/O I/O I/O I/O I/O I I O O Description Source port 1 TMDS positive inputs Source port 2 TMDS positive inputs Source port 1 TMDS negative inputs Source port 2 TMDS negative inputs Ground Source port 1 hot plug detector output Source port 2 hot plug detector output Sink port hot plug detector input Set to HIGH/LOW/OPEN Non Connect Pin Source port 1 DDC I2C clock line Source port 2 DDC I2C clock line 2 Sink port DDC I C clock line Source port 1 DDC I2C data line Source port 2 DDC I2C data line Sink port DDC I2C data line Source selector Power supply TMDS compliant voltage swing control (4.64k to GND) TMDS positive outputs TMDS negative outputs
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9/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Pin Assignment and Block Diagram of BU16018KV
A11 B11
RINT RINT TMD S RX
Technical Note
A12 B12
RINT VCC TMD S RX RINT
A13 B13
RINT VCC TMD S RX RINT
A14 B14
RINT VCC TMD S RX VCC RINT
TEST3 GND A34 B34 VCC A33 B33 GND A32 B32 VCC A31 B31 GND SCL3 SDA3 HPD3 VCC OE TEST2
VCC
A24 B24 A23 B23
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 HPD_SINK SDA_SINK SCL_SINK GND GND Z1 Y1 VCC Z2 Y2 GND Z3 Y3 VCC Z4 Y4 GND S3 S2 S1
RINT
RINT TMD S RX RINT TMD S RX RINT TMD S RX TMDS Drive TMDS Drive 3-to-1 MUX TMDS Drive
PRE VSADJ Y4 Z4 Y3 Z3 Y2 Z2 Y1
TMDS Drive
VCC RINT
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCC HPD2 SDA2 SCL2 GND GND B21 A21 VCC B22 A22 GND B23 A23 VCC B24 A24 GND VCC HPD1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VCC RINT
A22 B22 A21 B21 A34 B34 A33 B33 A32 B32 A31 B31 HPD1 HPD2 HPD3 SCL1 SDA1
VCC RINT RINT TMD S RX
Z1 OE S1 S2 S3
VCC RINT RINT TMD S RX RINT TMD S RX RINT TMD S RX RINT TMD S RX
BU16018KV
VCC RINT
VCC RINT
VCC RINT
HPD_SINK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TEST0 SDA1 SCL1 GND B11 A11 VCC B12 A12 GND B13 A13 VCC B14 A14 GND VCC VSADJ PRE TEST1
SCL2 SDA2 SCL3 SDA3
Control Logic
SCL_SINK SDA_SINK
Pin Explanation List Terminal Name A11, A12, A13, A14 A21, A22, A23, A24 A31, A32, A33, A34 B11, B12, B13, B14 B21, B22, B23, B24 B31, B32, B33, B34 GND HPD1 HPD2 HPD3 HPD_SINK TEST0,1,2,3
_______
OE PRE SCL1 SCL2 SCL3 SCL_SINK SDA1 SDA2 SDA3 SDA_SINK S1, S2, S3 VCC VSADJ Y1, Y2, Y3, Y4 Z1, Z2, Z3, Z4
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No. 6, 9, 12, 15 68, 71, 74, 77 49, 52, 55, 58 5, 8, 11, 14 67, 70, 73, 76 48, 51, 54, 57 4, 10, 16, 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 80 62 44 40 1, 20, 41, 60 42 19 3 64 46 38 2 63 45 39 21, 22, 23 7, 13, 17, 27, 33, 43, 50, 56, 61, 69, 75, 79 18 34, 31, 28, 25 35, 32, 29, 26
I/O I I I I I I O O O I I I I/O I/O I/O I/O I/O I/O I/O I/O I I O O
Description Port 1 TMDS positive inputs Port 2 TMDS positive inputs Port 3 TMDS positive inputs Port 1 TMDS negative inputs Port 2 TMDS negative inputs Port 3 TMDS negative inputs Ground Port 1 hot plug detector output Port 2 hot plug detector output Port 3 hot plug detector output Sink side hot plug detector input Open or GND connect (recommend) Output enable, active low TMDS high speed mode SW High : ON, Low : OFF (above 165MHz recommend to High) Source port 1 DDC I2C clock line Source port 2 DDC I2C clock line Source port 3 DDC I2C clock line Sink port DDC I2C clock line Source port 1 DDC I2C data line Source port 2 DDC I2C data line Source port 3 DDC I2C data line Sink port DDC I2C data line Source selector input Power supply TMDS voltage swing control. Connect to GND 4.64K TMDS positive outputs TMDS negative outputs
(c) 2010 ROHM Co., Ltd. All rights reserved.
10/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Pin Assignment and Block Diagram of BU16024KV
VSADJ OE PRE
VCC RINT
Technical Note
A4
Y4
TMDS Rx TMDS Driver
SDA_SINK
SCL_SINK
SELREF
VSADJ SCL
TEST3
TEST2
B4
VCC RINT
Z4
GND
GND
SDA
Vcc
Vcc
A3
36 35 34 33 32 31 30 29 28 27 26 25
Y3
TMDS Rx TMDS Driver
B3
24 23 22 21
Z3
VCC RINT
HPD GND B11 A11 Vcc B12 A12 GND B13 A13 Vcc NC
37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9
16024KV (48-pin VQFP)
20 19 18 17 16 15 14 13
HPD_SINK GND Z1 Y1 Vcc Z2 Y2 GND Z3 Y3 Vcc NC
A2 B2
VCC RINT
TMDS Rx TMDS Driver
Y2 Z2
A1 B1
TMDS Rx TMDS Driver
Y1 Z1
SCL
SCL_SINK
TEST0
TEST1
GND
PRE
GND
Vcc
I2CEN
OEB
B14
A14
Y4 Z4
SDA I2CEN SELREF HPD
SDA_SINK
HPD_SINK(* )
(*) when HPD_SINK = "L". Termination resistor is turned off.
Pin Explanation List Terminal Name No. B1, B2, B3, B4 39, 42, 45, 2 A1, A2, A3, A4 40, 43, 46, 3 Z1, Z2, Z3, Z4 22, 19, 16, 11 Y1, Y2, Y3, Y4 21, 18, 15, 10 HPD 37 HPD_SINK 24 SCL 34 SDA 33 SCL_SINK 27 SDA_SINK 28 VSADJ 35 I2CEN 6 SELREF 30 TEST0, 1, 2, 3 1, 12, 25, 36 N.C 13, 48 OEB PRE VCC GND 7 8 5, 14, 20, 29, 32, 41, 47 4, 9, 17, 23, 26, 31, 38, 44 I/O I I O O O I I/O I/O I/O I/O I I I I Description TMDS Negative inputs TMDS Positive inputs TMDS Negative outputs TMDS Positive outputs Source side hot plug detector output Sink side hot plug detector input Source port DDC I2C clock line Source port DDC I2C data line Sink port DDC I2C clock line Sink port DDC I2C data line TMDS voltage swing control(4.64k to GND) I2C Repeater enable Low : High-Z High : Active SCL_SINK/SDA_SINK Output voltage select Open or GND connect (recommend) Open or GND connect (recommend) TMDS Output enable Low : Active High : High-Z TMDS high speed mode SW High : ON, Low : OFF (above 165MHz recommend to High) Power supply Ground
I I -
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11/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Pin Assignment and Block Diagram of BU16027KV
A11 B11 A12 B12 A13 B13 A14 B14
Technical Note
A14 B14 Vcc A13 B13 GND A12 B12 Vcc A11 B11 SCL1 SDA1 HPD1 Reserve1 S2
RINT RINT TMD S RX
RINT
RINT
RINT
VCC TMD S RX
VCC TMD S RX
VCC
VCC
RINT
RINT
RINT
TMD S RX
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A24 B24
32 31 30 29 28 27
RINT
RINT TMD S RX RINT TMD S RX RINT TMD S RX TMDS Drive TMDS Drive TMDS Drive
Y4 Z4 Y3 Z3 Y2 Z2 Y1
TMDS Drive
VCC RINT
Reserve2 HPD2 SDA2 SCL2 B21 A21 Vcc B22 A22 GND B23 A23 Vcc B24 A24 HPD3
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
BU16027KV BU16028KV
(64-pin VQFP)
26 25 24 23 22 21 20 19 18 17
S1 HPD_SINK SDA_SINK SCL_SINK GND Z1 Y1 Vcc Z2 Y2 GND Z3 Y3 Vcc Z4 Y4
A23 B23 A22 B22 A21 B21 A34 B34 A33 B33 A32 B32 A31 B31 HPD1 HPD2 HPD3 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3
VCC RINT
VCC RINT RINT TMD S RX
VCC RINT RINT TMD S RX RINT TMD S RX RINT TMD S RX RINT TMD S RX
Z1 VSADJ
VCC RINT
VCC RINT
VCC RINT
S1 S2 HPD_SINK
SDA3 SCL3 GND B31 A31 Vcc B32 A32 GND B33 A33 Vcc B34 A34 GND VSADJ
1PIN MARK
Control Logic
SCL_SINK SDA_SINK
Pin Explanation List Terminal Name A11, A12, A13, A14 A21, A22, A23, A24 A31, A32, A33, A34 B11, B12, B13, B14 B21, B22, B23, B24 B31, B32, B33, B34 GND HPD1 HPD2 HPD3 HPD_SINK Reserve1 Reserve2 SCL1 SCL2 SCL3 SCL_SINK SDA1 SDA2 SDA3 SDA_SINK S1, S2 Vcc VSADJ Y1, Y2, Y3, Y4 Z1, Z2, Z3, Z4 No. 39, 42, 45, 48 54, 57, 60, 63 5, 8, 11, 14 38, 41, 44, 47 53, 56, 59, 62 4, 7, 10, 13 3, 9, 15, 22, 28, 43, 58 35 50 64 31 34 49 37 52 2 29 36 51 1 30 32, 33 6, 12, 19, 25, 40, 46, 55, 61 16 26, 23, 20, 17 27, 24, 21, 18 I/O I I I I I I O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O Description Source port 1 TMDS positive inputs Source port 2 TMDS positive inputs Source port 3 TMDS positive inputs Source port 1 TMDS negative inputs Source port 2 TMDS negative inputs Source port 3 TMDS negative inputs Ground Source port 1 hot plug detector output (status pin) Source port 2 hot plug detector output (status pin) Source port 3 hot plug detector output (status pin) Sink port hot plug detector input (status pin) In High, Low, and Open, any setting is OK. Non Connect Pin Source port 1 DDC I2C clock line Source port 2 DDC I2C clock line Source port 3 DDC I2C clock line Sink port DDC I2C clock line Source port 1 DDC I2C data line Source port 2 DDC I2C data line Source port 3 DDC I2C data line Sink port DDC I2C data line Source selector Power supply TMDS voltage swing control (via 4.64k to GND) Sink port TMDS positive outputs Sink port TMDS negative outputs
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12/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Source Selection Lookup Table of BU16006KV Control Pins I/O Selected HPD_SINK H H H H L L L L S1 H L L H H L L H S2 H H L L H H L L Y/Z A1/B1 Termination resistors of A2/B2 and A3/B3 are disconnected A2/B2 Termination resistors of A1/B1 and A3/B3 are disconnected Disallowed (indeterminate) State All termination resistors are disconnected None (Z) All termination resistors are disconnected Disallowed (indeterminate) State All termination resistors are disconnected Disallowed (indeterminate) State All termination resistors are disconnected Disallowed (indeterminate)State All termination resistors are disconnected None (Z) All termination resistors are disconnected SCL_SINK SDA_SINK SCL1 SDA1 SCL2 SDA2 None (Z) H SCL1 SDA1 SCL2 SDA2 None (Z) L L L L
Technical Note
Output Status HPD1 H L L HPD2 L H L H L L L L HPD3 L L H H L L L L
Source Selection Lookup Table of BU16027KV Control Pins I/O Selected HPD_SINK S1 S2 Y/Z A1/B1 Termination resistors of A2/B2 and A3/B3 are disconnected A2/B2 Termination resistors of A1/B1 and A3/B3 are disconnected A3/B3 Termination resistors A1/B1 and A2/B2 are disconnected None (Z) All terminations are disconnected SCL_SINK SDA_SINK SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Z)
Output Status HPD1 HPD _SINK HPD2 HPD3
H/L
H
H
L
L
H/L
L
H
L
HPD _SINK
L
H/L
L
L
L HPD _SINK
L HPD _SINK
HPD _SINK HPD _SINK
H/L
H
L
Source Selection Lookup Table of BU16018KV Control Pins I/O Selected HPD_SINK S1 S2 S3 Y/Z A1/B1 H H X X Termination resistors of A2/B2 and A3/B3 are disconnected A2/B2 H L H X Termination resistors of A1/B1 and A3/B3 are disconnected A3/B3 H L L H Termination resistors of A1/B1 and A2/B2 are disconnected None (Z) H L L L All terminations are disconnected Disallowed (indeterminate)State L H X X All terminations are disconnected Disallowed (indeterminate)State L L H X All terminations are disconnected Disallowed (indeterminate)State L L L H All terminations are disconnected None (Z) L L L L All terminations are disconnected H: Logic high; L: Logic low; X: Don't care; Z: High impedance
Output Status SCL_SINK/SDA_SINK HPD1 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Z) SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Z) H
HPD2 L
HPD3 L
L
H
L
L H L L L L
L H L L L L
H H L L L L
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13/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Equivalent Input And Output Schematic Diagrams
Technical Note
TMDS Input Stage VDD
TMDS Output Stage VDD VDD
HPD Output Stage VDD Ym Zm HPDn
50
50
Anm
Bnm
10mA
R-Side I2 C Input/Output Stage VDD SCL_SINK SDA_SINK SCL SDA
T-Side I2 C Input/Output Stage VDD
HPD_SINK
VDD
n=1,2,3 m=1,2,3,4
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14/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Note for use
Technical Note
1). Attention on use as "repeater" or "source" equipment. Y and Z terminals are connected to Vcc through ESD diode as Figure 7. When Vcc0.4 < AVcc, leak current flows from AVcc to Vcc. For this current, BU16006KV/BU16027KV can't pass the compliance test as "Repeater" and "Source" equipment (Test ID 7-3 VOFF). BU16018KV/BU16024KV is able to pass the compliance test using external element like Figure 8
Vcc=0V
Vcc=0V Voff Ym Ioff 50
AVcc=3.3V
Ioff
50 Zm Voff
AVcc=3.3V
Figure 7 TMDS Equivalent output schematic
Figure 8 Leak current control in BU16018KV and BU16024KV
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
15/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Technical Note
2). HPD_SINK Pull down resistance. HPD_SINK have a 5V tolerant structure shown in Figure 9.It needs some drive current to pull down HPD_SINK "H" to "L". So to pull down HPD_SINK, please use 10k(or under 10k) resistor.
Figure 9 HPD_SINK I/O schematic 3). About don't use terminal. 3-1. Unused TMDS input channel recommend open.
B U 1 6 0 * * KV
Vcc R INT R INT RT A TMDS Receiver TMDS Driver Y AVcc
B
Z
RT
Figure 10 TMDS Input Recommendation
3-2. Unused DDC Buffers of R side recommend to pull up to Vcc.
Vcc 4.7k SCL SDA R
T SCL_SINK SDA_SINK
Figure 11 Unused DDC Buffers of R side
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
16/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
3-3. Unused DDC Buffers of R side recommend pull up to Vcc.
Technical Note
Vcc 4.7k RSCL RSDA R T TSCL TSDA
Figure 12 Unused DDC of T side
3-4. Unused HPDn recommend open.
Figure 13 Open unused HPDn
4). About serial connection notice. When BU160xxKV output connect to other HDMI sw input like following application the specification of Jitter tolerance is downed. Especially when system needs 1080p (12bit) data rate and cable or PCB trace lengths between BU160xxKV input and output is small, Deteriorations of Jitter tolerance is outstanding. This problem also depends on receiver IC characteristic. When system is required 1080p (12bit), Rohm doesn't recommend serial connect application.
Figure 14 serial connection notice
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
17/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Technical Note
5). AC Coupling notice BU160xxKV can also communicate using AC coupling capacitor with TMDS line. But even connecting AC coupling capacitor, AC current may flow if input common mode voltage between two devices is different. For this current, the lower common mode voltage devices like PCIe or DP may be damaged by AC current.
Figure 15 AC Coupling connection notice
6). TMDS output offset voltage notice. Offset voltage may appear to TMDS output when there is no signal to TMDS input differential line. OE should set to "H" to avoid it.
7). Limitation of Master and slave direction as shown Figure 16.
Figure 16 Limitation of Master and slave direction
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18/19
2010.05 - Rev.E
BU16006KV, BU16018KV, BU16024KV, BU16027KV
Ordering part number
Technical Note
B
U
1
Part No. 16006 16018 16024 16027
6
0
0
6
K
V
-
E
2
Part No.
Package KV: VQFP80 (BU16018), VQFP64 (BU16027 / BU16006), VQFP48C (BU16024)
Packaging and forming specification E2: Embossed tape and reel
VQFP80
14.00.2 12.00.1
60 61 41 40

Tape Quantity Direction of feed
1.0 0.2
Embossed carrier tape (with dry pack) 1000pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
14.0 0.2
12.0 0.1
80 1 20
21
1.25
1.6MAX
1PIN MARK
+0.05 0.145 -0.03 S
4 +6 -4
1.4 0.05 0.1 0.05
0.08 S +0.05 0.2 -0.04 0.50.1 0.08
M
0.5 0.15
1.25
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
VQFP64
12.00.2 10.00.1
48 49 33 32

Tape Quantity Direction of feed Embossed carrier tape (with dry pack) 1000pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
12.00.2
10.00.1
0.50.15
64 1 16
17
1.25
1.6MAX
1PIN MARK
+0.05 0.145 -0.03
4 +6 -4
1.40.05 0.10.05
0.08 S +0.05 0.2 -0.04 0.50.1 0.08
M
1.00.2
1.25
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
VQFP48C
9.00.2 7.00.1
36 37 25 24

Tape Quantity Embossed carrier tape 1500pcs E2
direction the at left when you ( The on the leftishand1pin of product is thethe upperthe right hand hold ) reel and you pull out tape on
9.0 0.2
7.0 0.1
48 1 12
13
0.75
1.6MAX
1PIN MARK
+0.05 0.145 -0.03
4 +6 -4
1.4 0.05 0.1 0.05
0.50.1
0.08 S +0.05 0.22 -0.04 0.08
0.50.15
1.00.2
0.75
Direction of feed
M
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
19/19
2010.05 - Rev.E
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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